1. Field of the Invention
The present invention relates to a fabrication process for DRAM, and in particular to a bitline structure for DRAM and method of forming the same.
2. Description of the Related Art
Random access memory (RAM) is a volatile memory, usually categorized into static RAM (SRAM) and dynamic RAM (DRAM). SRAM stores information by the conductive state of the transistors in the memory cells, while digital signals from DRAM are determined by the charging states of capacitors in the memory cells. In RAM, information access is controlled by word lines connecting gates and bitlines that connect source/drain.
Conventional bitlines are mostly metal, with silicide preferred. Tungsten silicide and tungsten are the most widely used, as they exhibit high melting point, stability and low resistance.
FIG. 1 illustrates a cross section of a conventional bitline structure. 10 represents a substrate, 12 represents the dielectric layer, and 14, 20, 22, 24 are bitlines of metal, for example, tungsten. 16 represents a contact to bitline and 18 represents a peripheral contact.
The process for forming the above bitlines is shown as a flowchart in FIG. 2. A contact to bitline is first formed in a dielectric layer of a semiconductor substrate by photolithography and etching in step S10. Next, conductive material is filled in the contact to bitline in step S20. Etching back is then carried out in step S30 to lower the surface of the conductive material below the surface of the dielectric layer. Then, a peripheral contact is formed by photolithography and etching in step S40A. Exposure and etching are then performed to define bitlines. Next, a conductive material, such as tungsten, fills the contact to bitline and the peripheral contact to form bitlines. After completion of the bitlines, chemical mechanical polishing polishes the surface of the bitlines to create a smooth surface as illustrated in FIG. 1.
Shortcomings of the conventional process described above are overlapping bitlines due to high integration, causing shorts easily, illustrated as P between bitlines BL1 and BL2 in FIG. 6B. This adversely affects production yield.